Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a landing plug of the semiconductor device.
As an integration rate of a semiconductor memory device has been increased, a distance between gates has been decreased. Since an area occupying a contact hole has been reduced clue to the reduced distance between the gates, a process margin of the contact hole has been decreased. Technology to secure an improved process margin of the contact hole has been developed, and generally, a landing plug contact (LPC) process is used. The landing plug contact (LPC) process secures an overlay margin for a subsequent contact plug forming process by filling a space between gates to be formed, a bit line contact, and a storage node contact.
FIGS. 1A and 1B are cross-sectional views illustrating a method for fabricating a landing plug contact (LPC) of the conventional semiconductor device.
Referring to FIG. 1A, a plurality of gate patterns 12 are formed over a substrate 11. Then, a gate spacer 13 is formed on both sidewalls of the gate patterns 12.
Subsequently, an oxide layer (not illustrated) is formed as an interlayer dielectric layer 14 to cover an upper surface of the substrate 11. A photoresist pattern (not illustrated) is formed over the interlayer dielectric layer 14. A plurality of contact holes 15 are formed by etching the interlayer dielectric layer 14 using the photoresist pattern as an etch barrier layer.
Referring to FIG. 1B, an etch back process is performed on a conductive layer 16 for the landing plug contact (LPC) until an upper surface of the interlayer dielectric layer 14 is exposed, thereby forming a landing plug 16A.
However, since the conventional etch-back process for forming the landing plug 16A is performed using an anisotropic etch, a height difference between upper portions of the conductive layer 16 yields a height difference between upper portions of the landing plug 16A.
Furthermore, since a chlorine (Cl2) gas, having an etch rate with respect to a poly-silicon layer for the landing plug 16A greater than that with respect to an oxide layer for the interlayer dielectric layer 14, is used in an etch-back process, there is concern that the height difference between the upper portions of the landing plug 16A is becoming even larger.
The height difference between the upper portions of the landing plug 16A makes it difficult to control an etch amount and deposition thickness during a subsequent deposition process for forming a storage node contact plug and a bit line contact plug thereby decreasing a yield of the semiconductor memory device.